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Altera Corporation 31

MAX 7000 Programmable Logic Device Family Data Sheet

Tables 19 through 26 show the MAX 7000 and MAX 7000E AC

operating conditions.

Table 19. MAX 7000 & MAX 7000E External Timing Parameters Note (1)

Symbol Parameter Conditions -6 Speed Grade -7 Speed Grade Unit

Min Max Min Max

PD1

Input to non-registered output C1 = 35 pF 6.0 7.5 ns

PD2

I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns

Global clock setup time 5.0 6.0 ns

Global clock hold time 0.0 0.0 ns

FSU

Global clock setup time of fast input (2) 2.5 3.0 ns

Global clock hold time of fast input (2) 0.5 0.5 ns

CO1

Global clock to output delay C1 = 35 pF 4.0 4.5 ns

Global clock high time 2.5 3.0 ns

Global clock low time 2.5 3.0 ns

ASU

Array clock setup time 2.5 3.0 ns

Array clock hold time 2.0 2.0 ns

ACO1

Array clock to output delay C1 = 35 pF 6.5 7.5 ns

ACH

Array clock high time 3.0 3.0 ns

ACL

Array clock low time 3.0 3.0 ns

CPPW

Minimum pulse width for clear and

preset

(3) 3.0 3.0 ns

ODH

Output data hold time after clock C1 = 35 pF (4) 1.0 1.0 ns

CNT

Minimum global clock period 6.6 8.0 ns

CNT

Maximum internal global clock

frequency

(5) 151.5 125.0 MHz

ACNT

Minimum array clock period 6.6 8.0 ns

ACNT

Maximum internal array clock

frequency

(5) 151.5 125.0 MHz

MAX

Maximum clock frequency (6) 200 166.7 MHz

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 65 66

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