Cadence Q DRIVE SERIES Manual do Utilizador descarregar pdf (Página 8)

(ii) Define the top-level module for timing verification

Just like what you have done for Synthesis you need to define the top-level module for

timing verification.

Go to the “ac_shell” window and type the following:

ac_shell> set_top_timing_module $top

ac_shell> set_current_module $top

set_top_timing_module is a command that identifies the module, $top, to be used in

subsequent steps to apply timing constraints.

The module, $top, was the variable, my_design, in an earlier command.

set_current_module sets the module, $top, as the top-level current module.

(iii) Run the timing constraint script, timing.tcl

Just like what you have done for Synthesis you need to run the script file(s) for timing

verification.

To run the timing.tcl file, go to the “ac_shell” window and type the following:

ac_shell> source timing.tcl

To run the timing.tcl script type the following in the “ac_shell” window.

ac_shell> timing

(iv) Prepare the “timing report” template for timing verification tool,

“report.tcl”

You need to generate another file under “synthesis” directory that manages all the timing

related reports of your circuit following a timing verification step.

report.tcl file:

proc report {} {

mkdir report

mkdir netlist

report_timing > report/timing.rpt

report_area -hier -cell > report/area.rpt

report_hierarchy > report/hierarchy.rpt

write_verilog -hier netlist/my_design.net

}

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Cadence Q DRIVE SERIES Manual do Utilizador Página 8